This invention relates to the use of technology mapping for programming or designing a programmable logic device (“PLD”). In particular, this invention relates to using logical equivalency checking to find more efficient programming solutions for implementing user logic in a programmable logic device of a particular architecture, and also to find a more efficient architecture to implement a particular logical problem.
Programmable logic devices are well known. Early programmable logic devices were one-time configurable. For example, configuration may have been achieved by “blowing”—i.e., opening—fusible links. Alternatively, the configuration may have been stored in a programmable read-only memory. Those devices generally provided the user with the ability to configure the devices for “sum-of-products” (or “P-TERM”) logic operations. Later, such programmable logic devices incorporating erasable programmable read-only memory (EPROM) for configuration became available, allowing the devices to be reconfigured.
Still later, programmable logic devices incorporating static random access memory (SRAM) elements for configuration became available. These devices, which also can be reconfigured, store their configuration in a nonvolatile memory such as an EPROM, from which the configuration is loaded into the SRAM elements when the device is powered up. These devices generally provide the user with the ability to configure the devices for look-up-table-type logic operations.
While it may have been possible to program the earliest programmable logic devices manually, simply by determining mentally where various elements should be laid out, it was common even in connection with such earlier devices to provide programming software that allowed a user to lay out logic as desired and then translate that logic into programming for the programmable logic device. With current larger devices, it would be impractical to attempt to lay out the logic without such software.
One characteristic, however, of PLD programming software is that it is good at finding a solution that works—i.e., that implements the user logic design in a target PLD—but for certain user logic designs it may not find the best—i.e., the fastest or most efficient—solution, except by happenstance. A skilled user may even be able to recognize after the fact that, at least for a portion of the design, there is a better solution than the one found by the software. And while some PLD programming software provides a facility for a user to dictate a specific solution for at least a portion of the design—e.g., the QUARTUS® II software available from Altera Corporation, of San Jose, Calif., provides such a facility known as the “WYSIWYG Atom Mode”—those facilities are typically beyond the skill level of most users.
In addition, PLDs typically are designed to be as generic as possible. As a result, just as PLD programming software does not always find the best solution for implementing certain user logic designs, so too are PLD hardware designs not always optimal for certain user logic designs.
It would be desirable to be able to provide a method for programming a PLD that could find a more efficient solution for implementing at least a portion of a given user logic design. It also would be desirable to be able to provide a method for designing at least a portion of a PLD that is more optimal for a given user logic design.